Assistant Professor


Expert Areas : low-power Analog and Digital circuit design, biomedical microsystems, semiconductor devices and next generation computing

Kulbhushan Sharma received his B.E. in Electronics and Communication Engineering from Sant Longowal Institute of Engineering and Technology, Punjab, India, in 2011. He completed his doctorate degree from Chitkara University, Punjab, India, in 2020, the same place from where he completed his M.E. degree in 2016. He is working for the implementation of ultra-low-power analog front-end for non-invasive as well implantable neuro-electronics for brain machine interfaces. His current research interests lie in analog circuit design, semiconductor devices, implementation of ultra-low power analog front-end, biomedical microsystems, deep brain stimulations, neural prosthetics prototyping, silicon-photonics, energy-efficient computing.

During his PhD, he designed a neural amplifier IC chip which was released in Chitkara University campus on 28th, November 2020 in the presence of Dr. Madhu Chitkara (Pro Chancellor, Chitkara University), Dr. Archana Mantri (Vice Chancellor, Chitkara University) and Sh. H.S. Jatana (Group Head – Design and Process group, Semi-conductor Laboratory (SCL), India). This chip was designed at VLSI Centre of Excellence, Chitkara University and fabricated by Semi-conductor Laboratory (SCL), Punjab, India in 0.18 µm technology.
He has guided ME students and is currently guiding a PhD student.

He has authored 22 research articles in international Journals and Conferences. He has attended TENCON 2017 IEEE Region 10 Conference at Malaysia. He is active reviewer of IEEE Access, Circuit World, IEEE, International Journal of Electronics, India Council International conference (INDICON), International Conference on Wireless Networks and Embedded Systems (WECON).

  • Research
  • Teaching
  • Patents
  • Education
  • Service


  1. Thakur, D. and Sharma, K., 2022. 342 nW Class-AB Enhanced Flipped Source Follower Low Pass Filter for Biomedical Applications. Review of Scientific Instruments (Accepted)
  2. Sharma, K., Tripathi R. K., Jatana, H.S. and Sharma, R., 2022. Design of a low-noise low-voltage amplifier for improved neural signal recording. Review of Scientific Instruments, 93(6), 064710, DOI: https://doi.org/10.1063/5.0087527, Visit: https://doi.org/10.1063/5.0087527
  3. Madan, J., Tamersit, K., Sharma, K., Kumar, A., & Pandey, R. (2022). Performance Assessment of a New Radiation Microsensor Based 4H-SiC trench MOSFET: A Simulation Study. Silicon, 1-7. DOI: https://doi.org/10.1007/s12633-022-02084-w, Visit: https://link.springer.com/article/10.1007/s12633-022-02084-w
  4. Gundaboina, L., Badotra, S., Bhatia, T. K., Sharma, K., Mehmood, G., Fayaz, M., & Khan, I. U. (2022). Mining Cryptocurrency-Based Security Using Renewable Energy as Source. Security and Communication Networks, 2022, DOI: https://doi.org/10.1155/2022/4808703, Visit: https://www.hindawi.com/journals/scn/2022/4808703/
  5. Thakur, D., Sharma, K., Kapila, S., & Sharma, R., (2021). Ultra-low power signal conditioning system for effective biopotential signal recording. Journal of Micromechanics and Microengineering31(12), 124005,  DOI: 10.1088/1361-6439/ac3465, Visit: https://iopscience.iop.org/article/10.1088/1361-6439/ac3465/meta
  6. Saini, R., Sharma, K., & Sharma, R., (2021). A Low-Noise High-Gain Recycling Folded Cascode Operational Transconductance Amplifier Based on Gate Driven and Quasi-Floating Bulk Technique. Journal of Circuits, Systems and Computers, 2250099, DOI: https://doi.org/10.1142/S0218126622500992, Visit: https://www.worldscientific.com/doi/abs/10.1142/S0218126622500992
  7. Sharma, K., Pathania, A., Madan, J., Pandey, R. and Sharma, R., (2021) Process voltage temperature analysis of MOS based balanced pseudo-resistors for biomedical analog circuit applications. Circuit World., DOI: https://doi.org/10.1108/CW-08-2020-0213, Visit: https://www.emerald.com/insight/content/doi/10.1108/CW-08-2020-0213/full/html
  8. Sharma, K. and Sharma, R., 2021. Low-voltage low-noise gate driven quasi-floating bulk self-cascode current mirror operational transconductance amplifier. Review of Scientific Instruments92(3), 034717., DOI: https://doi.org/10.1063/5.0038939, Visit: https://aip.scitation.org/doi/10.1063/5.0038939
  9. Sharma, K., Pathania, A., Pandey, R., Madan J., & Sharma, R., (2021). MOS based pseudo-resistors exhibiting Tera ohms of incremental resistance for biomedical applications: analysis and proof of concept” Integration-the VLSI journal76, 25-39. DOI: https://doi.org/10.1016/j.vlsi.2020.08.001, Visit: https://www.sciencedirect.com/science/article/abs/pii/S0167926020302625
  10. Sharma, K., Jamuar, S. S., & Sharma, R., (2020). Design and Simulation of Pseudo-resistor with extremely high linearity for an improved Neural signal recording. Review of Scientific Instruments, 91(6), 066102. DOI: https://doi.org/10.1063/1.5125409, Visit: https://aip.scitation.org/doi/10.1063/1.5125409
  11. Sharma, P., Sharma, K., Jatana, H. S., Madan, J., Pandey, R., & Sharma, R. (2020). A 1.1 µW biopotential amplifier based on bulk-driven quasi-floating gate technique with extremely low-value of offset voltage. Analog Integrated Circuits and Signal Processing. 103(2), 303. DOI: https://doi.org/10.1007/s10470-020-01623-y, Visit: https://link.springer.com/article/10.1007%2Fs10470-020-01623-y
  12. Sharma, K., & Sharma, R. (2019). Design considerations for effective neural signal sensing and amplification: a review. Biomedical Physics & Engineering Express5(4), 042001. DOI: 10.1088/2057-1976/ab1674, Visit: https://iopscience.iop.org/article/10.1088/2057-1976/ab1674/meta
  13. Sharma, K., & Gupta, L. Implementation of Tunable and Non-Tunable Pseudo-Resistors using 0.18μm Technology (2016). International Journal of Computer Applications975, 8887, Vist:https://www.semanticscholar.org/paper/Implementation-of-Tunable-and-Non-Tunable-using-0.-Sharma-Gupta/82f1a1304b6523408956c12c192306f5573fa83f

Research papers in Conferences:

  1. Thakur, D., Sharma, K., & Sharma, R. (2022). Design of a Low-Noise Low-Power Fourth Order Complementary Super Source Follower Filter for EEG Applications. ECS Transactions, 107(1), 10969, Visit: https://iopscience.iop.org/article/10.1149/10701.10969ecst/meta
  2. Thakur, D., Sharma, K. and Sharma, R., (2021, May). Ultra Low-Power Low-Pass Filter Design for Wearable Biomedical Applications. In 2021 Devices for Integrated Circuit (DevIC)(pp. 629-632). IEEE,  Visit: https://ieeexplore.ieee.org/document/9455815
  3. Sharma, K., Tripathi, R., Jatana, H.S., Madan Jaya., Pandey R. & Sharma R. (2020, July) Current reference circuit operable at Low voltages using composite MOS triode resistor. VLSI DCS-2020: 2nd International Conference on VLSI Device, Circuit and System (DCS), Visit: https://ieeexplore.ieee.org/abstract/document/9179868
  4. Sharma, P., Sharma, K., Madan, J., Jatana H.S. & Sharma, R., (2020, July). Design of a low-power and low-noise gm-c filter for neural signal conditioning. VLSI DCS-2020: 2nd International Conference on VLSI Device Circuit and System (DCS), Visit: https://ieeexplore.ieee.org/document/9179856
  5. Sharma, K., Sharma, Y., Mantri, A. & Sharma, R., (2020, November). Inculcating the spirit and passion for research among Engineering students at Undergraduate level. Procedia Computer Science172, 488, DOI: https://doi.org/10.1016/j.procs.2020.05.162, Visit: https://www.sciencedirect.com/science/article/pii/S1877050920314927
  6. Sharma, K., Pathania, A., & Sharma, R. (2019, March). Analytical modelling and simulation of pseudo-resistive circuit techniques for biomedical applications. In 2019 Devices for Integrated Circuit (DevIC)(pp. 390-393). IEEE. DOI: 1109/DEVIC.2019.8783406, Visit: https://ieeexplore.ieee.org/abstract/document/8783406
  7. Singh, C. P., Pathania, A., Sharma, K., Madan, J., & Sharma, R. (2019, March). Design of an integrator-differentiator block for a transimpedance amplifier using 0.18µm technology. In 2019 Devices for Integrated Circuit (DevIC)(pp. 394-397). IEEE. DOI: 1109/DEVIC.2019.8783474, Visit: https://ieeexplore.ieee.org/abstract/document/8783474
  8. Sharma, P., Sharma, K., Jatana, H. S., & Sharma, R. (2019, March). A Low Power Biopotential Amplifier based on Bulk Driven Quasi Floating Gate Technique. In 2019 Devices for Integrated Circuit (DevIC)(pp. 424-427). IEEE. DOI: 1109/DEVIC.2019.8783245, Visit: https://ieeexplore.ieee.org/abstract/document/8783245
  9. Garg, D., Sharma, K., & Singla, A. (2018, December). Designing a Green Data Processing Device using Different Input/Output Standards on FPGA. In 2018 Fifth International Conference on Parallel, Distributed and Grid Computing (PDGC)(pp. 75-79). IEEE. DOI: 1109/PDGC.2018.8745716, Visit: https://ieeexplore.ieee.org/abstract/document/8745716
  10. Sharma, K., & Sharma, R. (2017, November). Highly consistent bulk driven quasi floating gate (BDQFG) PMOS pseudo-resistor design and implementation in 0.18 micron meter technology. In TENCON 2017-2017 IEEE Region 10 Conference(pp. 488-493). IEEE. DOI: 1109/TENCON.2017.8227913, Visit: https://ieeexplore.ieee.org/abstract/document/8227913
  11. Sharma, A., Sohal, H., & Sharma, K. (2016, October). Area and power analysis of adiabatic 2× 1 multiplexer design on 65nm CMOS technology. In 2016 5th International Conference on Wireless Networks and Embedded Systems (WECON)(pp. 1-6). IEEE. DOI: 1109/WECON.2016.7993489, Visit: https://ieeexplore.ieee.org/abstract/document/7993489
  12. Kaur, A., Pandey, B., Sharma, A., Sharma, K., & Singh, S. (2015, February). SSTL IO Standard Based Tera Hertz & Energy Efficient MALAYALAM Unicode Reader Design and Implementation on FPGA. In Bilingual International Conference on Information Technology: Yesterday, Today, and Tomorrow at Defence Scientific Information & Documentation Centre (DESIDOC), DRDO, Ministry of Defence, Government of India during(Vol. 6, No. 48), Visit:https://www.researchgate.net/publication/301542255_SSTL_IO_Standard_Based_Tera_Hertz_Energy_Efficient_MALAYALAM_Unicode_Reader_Design_and_Implementation_on_FPGA

Field of Specialisation

Design, layout and simulation of analog circuits for biomedical applications and its allied fields in CADENCE. Digital circuits design in Xilinx/Vivado. Field Programmable Gate Array (FPGA) and Semiconductor devices.

Training programs conducted

  • 3 Days Workshop on Analog Circuit Modelling and Simulations, Chitkara University, Punjab from 28-30 Sept., 2020.
  1. Circuit and a method for operating quasi floating bulk direct gate driven MOSFET. Patent No. 202211001806 12 January, 2022.
  2. Complementary super source follower metal oxide silicon field effect transistor-based filter Patent No. 202211002114 Dt. 13 January, 2022.
  3. Circuit for noise mitigation. Patent No. TEMP/E-1/14616/2020-DEL 28 March, 2020.
  4. Highly linear pseudo-resistive element Patent No. TEMP/E-121306/2020-DEL 09 May, 2022.
  5. Composite partial positive feedback-based system. Patent No. TEMP/E-1/48373/2020-DEL 07 October, 2022.

PhD (Electronics and Communication Engineering) from Chitkara University, Punjab, India
M. Tech (Electronics and Communication Engineering) from Chitkara University, Punjab, India
BE (Electronics and Communication Engineering) from Sant Longowal Institute of Engg.& Technology, Punjab, India

At various engineering colleges (2012 to 2022)
Education Leadership, Research management
10 years (2012 to date)