Dr Jaya Madan
Assistant Professor

jaya.madan@chitkara.edu.in

Expert Areas : Semiconductor Devices, Transistors, Device Modelling, TCAD Device Simulation, Solar Cell

Dr. Jaya Madan is currently an Assistant Professor (Research) at Chitkara University Research and Innovation Network (CURIN) Department of Chitkara University, Punjab, India. She received her B.Sc. (H) and M.Sc. degrees in Electronics from the University of Delhi, India, in 2011 and 2013 respectively. She received her doctorate (PhD) degree under the UGC (Government of India) JRF and SRF scheme in March 2018, from Applied Physics Department, Microelectronics Research Laboratory, Delhi Technological University (DTU) (Formerly Delhi College of Engineering), New Delhi, India. Her doctoral research involves modeling, design and simulation analysis of Gate All Around Tunnel FET for High Performance Analog and RF Applications.

During her PhD she has authored 10 peer-reviewed scientific international journal articles (SCI-indexed), 14 international conference articles, 01 national conference article and has also contributed to 01 springer book chapter. She is also the reviewer of many peer reviewed journals. Her research area covers the analytical modeling, designing and simulation of semiconductor devices such as field effect transistors, and solar cells.

  • Research
  • Teaching
  • Awards
  • Patents
  • Education
  • Service

Researcher IDs:

Field of Specialization

  1. Semiconductor Device Modeling, Simulation and Nanoelectronics.
  2. Expertise in TCAD designing of CMOS devices such as Tunnel FET, MOSFETs, junctionless FETs, HEMT for high performance analog and RF applications.
  3. Skilled in ATLAS SILVACO TCAD for designing Nano scale devices.
  4. Expertise in SCAPS, and AFORS-HET based solar cell device simulators.

Research Publications

Paper published in Journals and conferences:

  • Total Publications:45
  • 18               Papers in International Refereed Journals
  • 25               Papers in International Conferences
  • 01               Book Chapter
  • 01               National Conference

Chapter’s contributed in Books (1)

  1. Madan and R. Chaujar, “Effect of Nanoscale Structure on Reliability of Nano Devices and Sensors,” in Outlook and Challenges of Nano Devices, Sensors, and MEMS, T. Li and Z. Liu, Eds., ed Cham: Springer International Publishing, 2017, pp. 239-270.

Articles in International Refereed Journals (22) 

*Corresponding author

2020

  1. A. Pathania, J. Madan, R. Pandey, and R. Sharma, “Effect of structural and temperature variations on perovskite/Mg2Si based monolithic tandem solar cell structure,” Applied Physics A, vol. 126, p. 580, 2020/07/02 2020. (I.F.-1.810)
  2. R. Pandey, A. Khanna, K. Singh, S. K. Patel , H. Singh and J. Madan, “ Device Simulations: Toward the design of >13% Efficient PbS Colloidal Quantum Dot Solar Cell” Solar Energy, Elsevier, Accepted. (I.F.-4.608)
  3. J. Madan, R. Pandey, R. Sharma, and R. Chaujar, “Investigation of electrical/analog performance and reliability of gate metal and source pocket engineered DG-TFET,” Microsystem Technologies, Springer, DOI: https://doi.org/10.1007/s00542-020-04845-2, April 2020. Visit: https://link.springer.com/article/10.1007/s00542-020-04845-2
  4. P. Sharma, K. Sharma, H. Jatana, *J. Madan, R. Pandey, and R. Sharma, “A 1.1 µW biopotential amplifier based on bulk-driven quasi-floating gate technique with extremely low-value of offset voltage,” Analog Integrated Circuits and Signal Processing, Springer, DOI: https://doi.org/10.1007/s10470-020-01623-y, April 2020. Visit:https://link.springer.com/article/10.1007%2Fs10470-020-01623-y
  5. J. Madan, M. Dassi, R. Pandey, R. Chaujar and R. Sharma, “Numerical Analysis of Mg2Si/Si Heterojunction DG-TFET for low power/high performance applications: Impact of Non- Idealities,” Superlattices and Microstructures, Elsevier, vol. 139, p. 106397,2020.Visit: https://www.sciencedirect.com/science/article/pii/S0749603619318774
  6. J. Madan, R. Pandey and R. Chaujar, “Conducting Polymer based Gas Sensor using PNIN- Gate All Around – Tunnel FET,” Silicon, Springer, 2020. https://doi.org/10.1007/s12633-020-00394-5Visit:https://link.springer.com/article/10.1007/s12633-020-00394-5
  7. J. Madan, Shivani, R. Pandey, R. Sharma, “Device simulation of 17.3% efficient lead-free all-perovskite tandem solar cell,” Solar Energy, Elsevier, vol. 197, p. 212-221, 2020.Visit:https://www.sciencedirect.com/science/article/pii/S0038092X20300062
  8. J. Madan, S. Garg, K. Gupta, S. Rana, A. Manocha, and R. Pandey, “Numerical simulation of charge transport layer free perovskite solar cell using metal work function shifted contacts,” Optik, Elsevier, vol. 202, p. 163646, 2020. Visit:https://www.sciencedirect.com/science/article/pii/S003040261931544X

2019

  1. J. Madan, R. Pandey, R. Sharma, and R. Chaujar, “Impact of metal silicide source electrode on polarity gate induced source in junctionless TFET,” Applied Physics A, Springer, vol. 125:600, August 08 2019. Visit:https://link.springer.com/article/10.1007/s00339-019-2900-6
  2. R. Pandey, A. Singla, *J. Madan, R. Sharma, and R. Chaujar, “Toward the design of monolithic 23.1% efficient hysteresis and moisture free perovskite/c-Si HJ tandem solar cell: A numerical simulation study,” Journal of Micromechanics and Microengineering, IOP, vol. 29, p. 064001 (9pp), 2019.Visit:https://iopscience.iop.org/article/10.1088/1361-6439/ab1512/meta

2018

  1. S. Shekhar, J. Madan, and R. Chaujar, “Source/Gate Material-Engineered Double Gate TFET for improved RF and linearity performance: a numerical simulation,” Applied Physics A, Springer, vol. 124, p. 739, 2018. Visit: https://link.springer.com/article/10.1007/s00339-018-2158-4
  2. J. Madan and R. Chaujar, “Temperature Associated Reliability Issues of Heterogeneous Gate Dielectric – Gate All Around – Tunnel FET,” IEEE Transactions on Nanotechnology, vol. 17, no. 1, pp. 41-48, 2018, DOI: 10.1109/TNANO.2017.2650209. Visit:https://ieeexplore.ieee.org/abstract/document/7811198

2017

  1. J. Madan and R. Chaujar, “Numerical Simulation of N+ Source Pocket PIN-GAA-Tunnel FET: Impact of Interface Trap Charges and Temperature,” IEEE Transactions on Electron Devices, vol. 64, pp. 1482-1488, 2017. Visit:https://ieeexplore.ieee.org/abstract/document/7873327
  2. J. Madan and R. Chaujar, “Gate Drain Underlapped-PNIN-GAA-TFET for Comprehensively Upgraded Analog/RF Performance,” Superlattices and Microstructures, Elsevier,vol. 102, pp. 17-26, Feb. 2017. Visit: https://www.sciencedirect.com/science/article/pii/S0749603616314963
  3. J. Madan, R. Gupta, and R. Chaujar, “Mathematical modeling insight of hetero gate dielectric-dual material gate-GAA-tunnel FET for VLSI/analog applications,” Microsystem Technologies, Springer, vol. 23, pp. 4091-4098, September 01 2017. Visit:https://link.springer.com/article/10.1007/s00542-016-2872-9
  4. J. Madan, R. Gupta, and R. Chaujar, “Performance investigation of heterogeneous gate dielectric-gate metal engineered–gate all around-tunnel FET for RF applications,” Microsystem Technologies, Springer, vol. 23, pp. 4081-4090, September 01 2017. Visit:https://link.springer.com/article/10.1007/s00542-016-3143-5

2016

  1. J. Madan and R. Chaujar, “Interfacial Charge Analysis of Heterogeneous Gate Dielectric-Gate All Around-Tunnel FET for Improved Device Reliability,” IEEE Transactions on Device and Materials Reliability, vol. 16, pp. 227-234, 2016. Visit:https://ieeexplore.ieee.org/abstract/document/7466102
  2. J. Madan and R. Chaujar, “Palladium gate all around-Hetero dielectric-tunnel FET based highly sensitive hydrogen gas sensor,” Superlattices and Microstructures, Elsevier,vol. 100, pp. 401-408, 2016. DOI: http://dx.doi.org/10.1016/j.spmi.2016.09.050.Visit:https://www.sciencedirect.com/science/article/pii/S0749603616305262
  3. J. Madan and R. Chaujar, “Gate drain-overlapped-asymmetric gate dielectric-GAA-TFET: a solution for suppressed ambipolarity and enhanced ON state behavior,” Applied Physics A, Springer,vol. 122, p. 973, 2016.Visit:https://link.springer.com/article/10.1007/s00339-016-0510-0

2015

  1. J. Madan, R. Gupta, and R. Chaujar, “Analytical drain current formulation for gate dielectric engineered dual material gate-gate all around-tunneling field effect transistor,” Japanese Journal of Applied Physics,IOP, vol. 54, p. 094202, 2015. Visit:https://iopscience.iop.org/article/10.7567/JJAP.54.094202/meta

 

Articles in International Conferences (27)

2020

  1. S. Sharma, S. Gohri, R. Pandey*, J. Madan and R. Sharma, “Device Simulation of Poly (3-hexylthiophene) HTL Based Single and Double Halide Perovskite Solar Cells,” in IEEE 47th Photovoltaic Specialists Conference (PVSC), 2020 (Accepted).
  2. S. Gohri, S. Sharma, R. Pandey*, J. Madan and R. Sharma, “Influence of SnS and Sn2S3 based BSF layers on the performance of CZTSSe solar cell,” in IEEE 47th Photovoltaic Specialists Conference (PVSC), 2020 (Accepted).
  3. A. Pathania, R. Pandey*, J. Madan and R. Sharma, “Performance evaluation of lead-free perovskite solar cell with different Hole/Electron transport materials,” in IEEE 47th Photovoltaic Specialists Conference (PVSC), 2020 (Accepted).
  4. P. Sharma, J. Madan, S. Mann, A. Mantri, and R. Sharma, “Studies on the Outcome and Relevance of Research in Artificial Intelligence Domain in South Asian Subcontinent”, in Procedia Computer Science, volume 172, pp. 616-622, 2020.
  5. M. Dassi, *J. Madan, R. Pandey and R. Sharma, “Effect of temperature on analog performance of Mg2Si source heterojunction double gate tunnel field effect transistor”, International Conference on Aspects of Materials Science and Engineering (ICAMSE 2020), 29-30th May, 2020, Panjab University, Chandigarh, India. (Accepted).

2019

  1. J. Madan, R. Pandey, R. Sharma, S. Shekhar and R. Chaujar, “Built-in reliability investigation of gate-drain underlapped PNIN-GAA-TFET for improved linearity and reduced intermodulation distortion”, 6th International Conference on ‘Microelectronics, Circuits and Systems’, Micro2019, 06-07th July, 2019, Amity University, Kolkata, India. (Presented).
  2. R. Pandey, J. Madan, R. Sharma, and R. Chaujar, “Numerical Simulations to Understand the Role of DIO Additive in PTB7: PC 71 BM Solar Cell,” in 2019 IEEE 46th Photovoltaic Specialists Conference (PVSC), 2019, pp. 0484-0486.Visit: https://ieeexplore.ieee.org/document/8980682
  3. Shivani, Madan, R. Pandey, and R. Sharma, “Designing of CZTSSe Based SnS Thin Film Solar Cell for Improved Conversion Efficiency: A Simulation Study with SCAPS,” in 2019 IEEE 46th Photovoltaic Specialists Conference (PVSC), 2019, pp. 0193-0195.Visit: https://ieeexplore.ieee.org/document/8980459
  4. A. Pathania, R. Pandey, J. Madan, and R. Sharma, “Design and Simulation of Novel Perovskite/Mg 2 Si Based Monolithic Tandem Solar Cell With 25.5% Conversion Efficiency,” in 2019 IEEE 46th Photovoltaic Specialists Conference (PVSC), 2019, pp. 1049-1051.Visit:https://ieeexplore.ieee.org/document/8980777
  5. C. P. Singh, A. Pathania, K. Sharma, J. Madan, R. Sharma, “Design of an Integrator-Differentiator Block for a Transimpedance Amplifier Using 0.18µm Technology”, pp.-394-397, 2019 Devices for Integrated Circuit (DevIC), 23-24 March, 2019, Kalyani, India.Visit: https://ieeexplore.ieee.org/document/8783474

2018

  1. J. Madan, H. Arora, R. Pandey and R. Chaujar, “Analysis of Varied Dielectrics as Surface Passivation on AlGaN/GaN HEMT for Analog Applications”, International Conference on Wireless Networks & Embedded Systems (WECON-2018), pp. 15-18, 16-17, November 2018, Chitkara University, Punjab, India. 978-1-5386-7050-7/18/$31.00 ©2018 IEEE. (Best Paper Award)https://ieeexplore.ieee.org/document/8782074
  2. R. Kaur, J. Madan, R. Sharma, R. Pandey and R. Chaujar, “Capacitive Analysis of Hetero Material Gate PNIN-DG-TFET over Diverge Temperature Range for Superior RF/Microwave Performance”, The 2018 IEEE Electron Device Kolkata Conference (2018 IEEE EDKCON), pp.-252-257, 24-25, November 2018, at Kolkata, India. https://ieeexplore.ieee.org/document/8770491
  3. A. Singla, R. Pandey, R. Sharma, J. Madan, K. Singh, V. K. Yadav and R. Chaujar, “Numerical Simulation of CeOx ETL based Perovskite Solar Cell: – An optimization study for high efficiency and stability”, The 2018 IEEE Electron Device Kolkata Conference (2018 IEEE EDKCON), pp.-278-282, 24-25, November 2018, at Kolkata, India. https://ieeexplore.ieee.org/document/8770401
  4. J. Madan, R. Kaur, R. Sharma, R. Pandey and R. Chaujar, “Electrical Characteristics Assessment of Gate Metal and Source Pocket Engineered DG-TFET for low Power Analog Applications”, The 2018 IEEE Electron Device Kolkata Conference (2018 IEEE EDKCON), pp.-358-362, 24-25, November 2018, at Kolkata, India.https://ieeexplore.ieee.org/document/8770462
  5. N. Arora, R. Pandey, R. Sharma, J. Madan and R. Chaujar, “Parametric Variation of ZnSe/TiO2 Electron Transport Layer Based Perovskite Solar Cell: A Simulation Study and Optimization”, The 2018 IEEE Electron Device Kolkata Conference (2018 IEEE EDKCON), pp.-428-432, 24-25, November 2018, at Kolkata, India.https://ieeexplore.ieee.org/document/8770451
  6. H. Arora, J. Madan, and R. Chaujar, “Impact On Analog And Linearity Performance Of Nanoscale AlGaN/GaN HEMT With Variation In Surface Passivation Stack,” Materials Today: Proceedings, Elsevier, vol. 5, pp. 17464-17471, 2018.Visit: https://www.sciencedirect.com/science/article/pii/S221478531831160X
  7. J. Madan, R. Pandey, and R. Chaujar, “Gate Drain Underlapping: A Performance Enhancer For HD-GAA-TFET,” Materials Today: Proceedings, Elsevier, vol. 5, pp. 17453-17463, 2018. Visit:https://www.sciencedirect.com/science/article/pii/S2214785318311593
  8. J. Madan, K. Karwal, and R. Chaujar, “Performance Analysis of Heterojunction DMDG-TFET with Different Source Materials for Analog Application”, pp.-1474-1478, International Conference on Trends in Electronics and Informatics (ICOEI 2018), 11-12, May 2018 at Tirunelveli, India.https://ieeexplore.ieee.org/document/8553716
  9. J. Madan, S. S. Bisht, and R. Chaujar, “Heterojunction DG-TFET –Analysis of Different Source Material for Improved Intermodulation”, pp.-1080-1084, International Conference on Trends in Electronics and Informatics (ICOEI 2018), 11-12, May 2018 at Tirunelveli, India.https://ieeexplore.ieee.org/document/8553856

2017

  1. J. Madan, S. Shekhar and R. Chaujar, “Gate Metal Engineered Heterojunction DG-TFETs for Superior Analog Performance and Enhanced Device Reliability”, in Conference on Information and Communication Technology CICT-2017, IIITM Gwalior, India, November 3-5, 2017, pp-1-4, DOI-10.1109/INFOCOMTECH.2017.8340634, Electronic ISBN:978-1-5386-1866-0.  https://ieeexplore.ieee.org/document/8340634
  2. J. Madan, S. Shekhar, and R. Chaujar, “PNIN-GAA-tunnel FET with palladium catalytic metal gate as a highly sensitive hydrogen gas sensor,” in Simulation of Semiconductor Processes and Devices (SISPAD), 2017 International Conference on, 2017, pp. 197-200.https://ieeexplore.ieee.org/document/8085298
  3. J. Madan, S. Shekhar and R. Chaujar, “Source Material Assessment of Heterojunction DG-TFET for Improved Analog Performance”, in International Conference on Microelectronics Devices, Circuits and Systems (ICMDCS 2017), VIT University, Vellore India, 10-12th August 2017.https://ieeexplore.ieee.org/document/8211532
  4. J. Madan and R. Chaujar, “Influence of Temperature Variations on Radio Frequency Performance of PNIN Gate All Around Tunnel-FET”, in International Conference on 2ndIEEE International Conference on Recent Trends in Electronics, Information & Communication Technology (RTEICT – 2017), pp. 1110-1114, Bengaluru, India, 19-20 May 2017, DOI: 978-1-5090-3704-9.https://ieeexplore.ieee.org/document/8256772

2016

  1. J. Madan and R. Chaujar, “Temperature associated reliability issues of heterogeneous gate dielectric-gate all around-tunnel FET,” in Nanoelectronics Conference (INEC), 2016 IEEE International, Chengdu, China, 9-11 May, 2016, pp. 1-2, DOI:10.1109/INEC.2016.7589278.https://ieeexplore.ieee.org/document/7589278

2015

  1. J. Madan, R.S. Gupta and R. Chaujar, “Impact of Heterogeneous Gate Dielectric and Gate Metal Engineering on Analog and RF Performance of GAA TFET,” in 18th International Workshop on Physics of semiconductor devices, (IWPSD-2015), 7-10th December, 2015.
  2. J. Madan, R.S Gupta, R. Chaujar. “Capacitive Analysis of Heterogeneous Gate Dielectric-Gate Metal Engineered–Gate All Around-Tunnel FET for RF Applications,” in 2nd International conference on Microelectronics, circuits and systems, Micro-2015, Vol. 1, pp.6-10, Kolkata, 11-12th July, 2015, ISBN-81-85824-46-0.
  3. J. Madan, R.S Gupta, R. Chaujar. “Drain current Analysis of Hetero Gate Dielectric-Dual Material Gate–GAA-Tunnel FET,” in 2nd International conference on Microelectronics, circuits and systems, Micro-2015, Vol. 2, pp.57-61, Kolkata, 11-12th July, 2015, ISBN-81-85824-46-0.
  4. J. Madan, R.S Gupta, R. Chaujar, “TCAD Analysis of Small Signal Parameters and RF Performance of Heterogeneous Gate Dielectric-Gate All Around Tunnel FET,” Tech Connect World Innovation Conference and Expo, Chapter 6, “Nanoelectronics, Materials and Devices”, pp.189-192, June 14-17, 2015, Gaylord National Resort and Convention Center, National Harbor, Maryland, just outside of Washington, D.C., U.S.A. Visit: https://briefs.techconnect.org/papers/tcad-analysis-of-small-signal-parameters-and-rf-performance-of-heterogeneous-gate-dielectric-gate-all-around-tunnel-fet/
  5. J. Madan, R.S Gupta, R. Chaujar, “Threshold voltage model of a Hetero Gate Dielectric Dual Material Gate GAA Tunnel FET,” Tech Connect World Innovation Conference and Expo, Chapter 7, “Modeling and Simulation of Microsystems”, pp.254-257, June 14-17, 2015, Gaylord National Resort and Convention Center, National Harbor, Maryland, just outside of Washington, D.C., U.S.A. Visit: https://briefs.techconnect.org/papers/threshold-voltage-model-of-hetero-gate-dielectric-dual-material-gate-gaa-tunnel-fet/

 

Articles in National Conferences (1)

  1. J. Madan and R. Chaujar. “Source Pocket Parameters Assessment of PNIN-GAA-TFET for Improved Analog Performance and High Switching Speed Applications,” in 2nd Second National Conference on Recent Developments in Electronics (NCRDE-2017), Delhi, pp. 77-83, 17th to 18th February, 2017.

Other Research Related Activities

  1. Member of publication committee of 6th International Conference on Wireless Networks & Embedded Systems WECON 2018 held at Chitkara University during 16th -17th Nov, 2018, Punjab, India.
  2. Served as a Resource person in STEAM School, and shared expertise in the workshop for 10 days on solar cell device simulation during January-April 2019, organized by Chitkara university research and innovation network (CURIN), Chitkara university, Punjab.
  3. Served as the Resource Person and shared research expertise to other faculty members on the subject matter during 10 days Faculty Development Program on “State of Art Electronic Circuits/Devices and their Applications, Photonics”, from 25th June 2018 to 6th July 2018, in Chitkara University.
  4. Member of DRC committee at Chitkara University, Punjab.

 Overseas research paper presentation

  1. Present 03 Research papers in “46th IEEE Photovoltaic Specialists Conference (46th PVSC)”, during June 16-21, 2019, at Sheraton grand Chicago, IL, USA. (Sponsored by SERB, DST)
  2. Presented (orally) part of research work in “the INEC-2016 Conference, 7th IEEE International Nanoelectronics Conference” held on 09th -11th May, 2016 at Chengdu, China. Titled “Temperature associated reliability issues of heterogeneous gate dielectric-gate all around-tunnel FET”. Sponsored by Delhi Technological University, Delhi.

Active Reviewer of

1. IEEE Transactions on Electron Devices.
2. IET Circuits, Devices & Systems.
3. IET, Micro & Nano Letters.
4. Vacuum, Elsevier.
5. Journal of Computational Electronics, Springer.
6. Taylor & Francis, International Journal of Modelling and Simulation.
7. Journal of Nanoelectronics and Optoelectronics, ASP.
8. Indian Journal of Physics, Springer.
9. AEÜ – International Journal of Electronics and Communications, Elsevier.
10. Results in Physics, Elsevier.
11. Semiconductor Science and Technology, IOP.
12. Physica E: Low-dimensional systems and nanostructures, Elsevier.
13. IEEE 40th International Conference on Electronics and Nanotechnology (ELNANO-2020)

Field of Specialisation:

Solid State Physics, Analog Electronics, Digital Electronics, Semiconductor Materials and Devices, Physics of Semiconductor Devices, Basics of Electronics Engineering, Fundamentals of Electronic Devices are mainly interesting subject for the teaching at both UG and PG level.

Ongoing M.E. Thesis Guidance:

  1. One M.E. Student of batch 2018-Solar cell simulation using SCAPS-1D simulator.

Ongoing Ph.D. Research Guidance

  1. “Double gate Tunnel FETs” – Minaxi Dassi (Joined in December 2016)
  2. “Charge plasma TFET” – Preeti Sharma (Joined in August 2019)
  3. “Si PERC Solar cells” – Savita (Joined in August 2019)

Academic Events

  1. Attended and presented research work in “46th IEEE Photovoltaics Specialist Conference (PVSC)” held at the Sheraton Grand, Chicago, IL USA, June 16-21, 2019.
  2. Attended and presented research work in “International Conference on Wireless Networks & Embedded Systems (WECON-2018)” held at the Chitkara University, Punjab, India, November 16-17, 2018.
  3. Attended and presented research work in “The 2018 IEEE Electron Device Kolkata Conference (2018 IEEE EDKCON)” held at the Pride Hotel, Kolkata, India, November 24-25, 2018.
  4. Attended and presented research work in “Conference on Information and Communication Technology CICT-2017”, held at IIITM Gwalior, India, November 3-5, 2017.
  5. Attended and presented research work in “2ndIEEE International Conference on Recent Trends in Electronics, Information & Communication Technology (RTEICT – 2017)”, held at Sri Venkateshwara College of Engineering, Bengaluru, India, May 19-20, 2017.
  6. Attended and presented research work in “IEEE International Nanoelectronics Conference (INEC), 2016”, held at Chengdu, China, May 9-11, 2016.
  7. Attended and presented research work in “18th International Workshop on Physics of semiconductor devices, (IWPSD-2015)”, held at Indian Institute of Science, Bangalore, India, 7-10th December, 2015.
  8. Attended and presented research work in “2nd International conference on Microelectronics, circuits and systems, Micro-2015”, held at Hotel Hyatt Regency in Kolkata, India, 11-12th July, 2015.
  9. Participated in the One Day National Seminar on Frontiers in Applied Science and Technology (FAST-2016) held on 22nd March 2016 at Delhi Technological University.
  10. Participated in the TEQIP-II Sponsored One Week Faculty Development Programme on “Advances in microelectronics and plasma diagnostics” from 29th August to 2nd September 2016, at Delhi Technological University.
  11. Participated in the workshop titled “E-Resources: A Gateway for Research” held from 05th September to 09th September 2016, at Delhi Technological University.
  12. Participated in the Quad copter UAV program held at Delhi Technological University of Robothlon-2015.
  13. Participated in the One Week Faculty Development Program under TEQIP-II on “Recent Advances and Challenges in Power and Energy for Sustainable Growth” held during 01st June to 05th June 2015, at Delhi Technological University.
  14. Participated in the “National Workshop on Power Electronics (NWPE-2015)” held during 06th November to 07th November 2015, at Delhi Technological University.
  15. Participated in the UGC sponsored one day National seminar on Recent Advance in Physics (NSRAP-2015) held at Delhi Technological University on 16th, 2015.
  16. Participated in the workshop titled “Emerging trends in electronics ELECTRAWORK-2009” held from 01st June to 12th June 2009, Acharya Narendra Dev College, Delhi University.
  17. Attended Tutorial on ESD Challenges in Sub-micron Devices: Design, Testing and Application, held on January 19, 2013 as part of First National Conference on Recent Developments in Electronics (NCRDE-2013), organised by IEEE-EDS Delhi Chapter at University of Delhi South Campus, New Delhi.
  18. Attended Second National Workshop on “Einstein and Special Theory of Relativity” held in Deen Dayal Upadhyaya College, University of Delhi, on November 07, 2009.
  19. Participated in the National Workshop on “Fibre Optics and Application” held in SP Jain Centre, University of Delhi South campus on 28th -29th November 2009.
  1. Received “Excellence awards Chitkara University 2020” for publishing a research paper with highest H-Index in Chitkara university as first author during the calendar year 2019, on 15th February 2020.
  2. Received “Research Publication Incentive Award” on 27th July, 2019 for excellence in research during January-June 2019, Chitkara University.
  3. Received Financial Assistance by DST SERB under “International travel support (ITS)” scheme to present and attend the international scientific event “46th IEEE Photovoltaic Specialists Conference (PVSC 46) 2019, held at Chicago, USA from 16 June, 2019 to 21 June, 2019.
  4. Received “Teacher’s Excellence Award under Most Committed Category” during excellence awards in April 2019, Chitkara University.
  5. Received “Research Publication Excellence Award” during excellence awards in April 2019, Chitkara University.
  6. Received “Outstanding Ph.D. Thesis Award”, in the VLSI field, in the International Conference on Signal Processing, VLSI and Communication Engineering (ICSPVCE-2019), Delhi Technological University, March 2019.
  7. Awarded prize money and certificate for “Commendable Research Awardfor excellence in research, in recognition for the research during the year 2018, DTU.
  8. ReceivedBest Paper Awardin International Conference on Wireless Networks & Embedded Systems (WECON-2018), 16-17, November 2018, at Chitkara University, Punjab, India.
  9. Awarded Prize Money and Certificate of “Premier Research Awardfor excellence in research, in recognition for the research during the year 2017, DTU.
  10. Awarded prize money and certificate for “Commendable Research Awardfor excellence in research, in recognition for the research during the year 2017, DTU.
  11. Received Travel Grant by Delhi Technological University for Oral Presentation of part of research work in “7th IEEE International Nanoelectronics Conference-INEC 2016” Chengdu, China.
  12. UGC–NET-JRF (June-2013) QUALIFIED (Lectureship & Fellowship)
  13. Awarded shield and Certificate of Merit for securing 3rd Position in Delhi University, in 3rd Year, B.Sc. (H) Electronics.
  14. Awarded with certificate of Merit for securing 1st position in college in 1st year B.Sc. (Hons.) Electronics, Delhi University, 2009.
  15. Awarded with certificate of Merit for securing 1st position in college in 2nd year B.Sc. (Hons.) Electronics, Delhi University, 2010.
  16. Awarded with certificate of Merit for securing 1st position in college in 3rd year B.Sc. (Hons.) Electronics, Delhi University, 2011.

PATENT FILED:
1. Pandey, R; Madan, J; and The Chitkara University, Punjab 2020, Charge Plasma Perovskite Solar Cell Device| Patent Application No. 202011022005, Published 02/06/2020.

PhD: Applied Physics, Delhi Technological University, New Delhi, India, August 2013 to March 2018.

Dissertation Title: Simulation and Analysis of Gate All Around Tunnel FET For High Performance Analog and RF Applications.

M.Sc. : Electronics, University of Delhi, India, June 2013

B.Sc. : Electronics, University of Delhi, India, June 2011

  1. From 17th January 2018 to 17th May 2018, worked as an Assistant Professor in ABES Institute of Technology (ABESIT), Ghaziabad, UP.
  2. From October-2015 to December 2017, worked as a Senior Research Fellow (SRF), under UGC-JRF Fellowship scheme in Department of Applied Physics, Delhi Technological University, DTU.
  3. From August-2013 to October-2015, worked as Junior Research Fellow (JRF), under UGC-JRF Fellowship scheme in Department of Applied Physics, Delhi Technological University, DTU.
  4. From August 2013 to December 2017 involved with undergraduate lab classes of Microprocessor 8086 and analog and digital communication of 1st year and 3rd year students as a Research Assistant in Department of Applied Physics, Delhi Technological University.