Inventors have developed 32 X 64 bit QCA based SRAM using eleven input majority gates and successfully designed addressing circuitry i.e. 32:1 multiplexer and 4 X 32 decoders for the memory design. This newly developed 32 X 64 bit SRAM can be designed from lesser number of QCA cells thereby reducing the circuit complexity and lesser area is thus occupied as compared to the existing technology.
Inventors
Rupinder Kaur, Nitin Saluja
